Press Release  


Eureka Technology Unveils PCI Express Bus Controller IP Cores

LOS ALTOS, CA., November 17, 2003 - Eureka Technology Inc, a leading intellectual property (IP) core provider, today announces the immediate availability of its latest PCI Express Bus Controller Core. This IP core is compliant with the industrial standard PCI Express bus specification and is fully synthesizable for ASIC and FPGA designs. It is available in both Verilog and VHDL format.

PCI Express bus offers very high data bandwidth over existing bus standards. The backward compactibility and scalability of the PCI Express bus makes it an ideal bus interface for the next generation high performance system designs. However, the complexity of the specification makes adaptation to this new bus standard a very challenging task. Eureka Technology solves this problem by providing a PCI Express IP core that handles all the complex PCI bus protocols and presents a very simple interface to the user. User of this core can access data across the PCI Express bus as simple as reading or writing local memory or I/O data.

"Eureka Technology has many years of experience in providing silicon proven bus interface IP cores to its customers, including all versions of PCI bus bridges." said Simon Lau, President of Eureka Technology. "By leveraging on our expertise in bus interface development, we are able to design a PCI Express bus interface core that provide high performance, low risk and cost effective PCI Express solution for our customers. This core strengthens our product portfolio in the bus interface area and we will continue to add PCI and PCI Express bridges to our product offerings."

About The PCI Express Core

The PCI-Express Bus Controller core is designed for efficient and flexible integration with user designed logic. The controller utilizes multiple data buffers to minimize gate count and allows processing of multiple requests in pipeline manner to achieve highest possible data bandwidth. The PCI-Express Bus Controller core is a PCI end-point core that supports 1 to 4 data lanes up to 10Gbps. As a transmitter, the core is capable of initiating memory, IO, and message request upon user requests. The core automatically constructs the packet to be sent across the PCI Express link by adding required data fields such as CRC, sequence number, tag and requester ID. As a receiver, the core interprets the packets it receives from the PCI link, performs all the protocol and error checking and generates the proper acknowledge signal. The received data or commands are then forwarded to the user interface as regular memory or IO access. For more information about the core, please visit the web page at

About Eureka Technology

Eureka Technology is a leading intellectual property (IP) provider for ASIC and FPGA designs. The company offers a wide range of silicon-proven system core logic functions and peripheral functions to support different bus standards and CPU interfaces, including PCI™, PCI Express™, Cardbus™, PowerPC™, ARM™, MIPS™, ARC™, SH2/3/4™, DDR_SDRAM, CompactFlash and PCMCIA™. These IP cores are designed to improve the design time-to-market delay, eliminate design risks, and reduce development costs for System-on-Chip (SoC) designs. Founded in 1993, the company has a strong customer base in the United States, Japan and Europe. For more information about the company, please visit its web site at or send email to