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Peripheral Controller for ARCtangent
This memory and peripheral controller IP core interfaces between the ARCtangent processor's arbitration unit and provides access to external
SDRAM, FLASH, and PCI host bridge and peripheral slave devices defined by user. It is optimized to serve as memory sequencer
for the ARCtangent core architecture. It automatically handles SDRAM and FLASH timing such as row and column latency, precharge
timing, and data burst length. All these timing parameters are set by the memory controller on system reset and can be programmed by
the user during run-time to optimize system performance.
- Mapped to multiple access destinations.
- Shares external address and data bus for SDRAM, FLASH and user logics.
- Byte collection for narrowidth FLASH devices.
- Programmable access timing parameter for all devices.
ARCtangent to PCI Host Bridge
This PCI host bridge IP core contains the bus master, bus target, and configuration initiator function, to support instruction transfer in both
directions allowing an ARCtangent processor core to initialize and access devices on the PCI (specification 2.2 protocol) bus and allows a remote
PCI bus master to access the system internal resources through the client interface and memory arbitration units. The host bridge
operates in two clock domains, the CPU bus clock and the PCI bus clock - the two clock domains can be asynchronous to each other. Single
and burst data transfers are supported both as bus master and bus target.
- Compliant with PCI spec 2.2.
- Upstream and downstream data transfer.
- ARCtangent and PCI bus runs at different clock domains.
- Multiple data buffer to speed up data transfer.
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Peripheral
Controller for ARCtangent