EP453 ARCtangent to PCI Host Bridge

Features

• Fully supports PCI specification 2.2 protocol.
• Designed for ASIC and FPGA implementations in various system environments.
• Combined PCI bus master, bus target, and configuration access functions in one core.
• 32-bit bus master and target support.
• Supports burst transfer to maximize memory bandwidth.
• Zero wait state PCI data transfer. Up to 133Mbyte/sec at 33Mhz and 266Mbyte/sec at 66Mhz.
• Supports target retry, disconnect and target abort.
• Automatic transfer restart on target retry and disconnect.
• Concurrent bus master and target function.
• Generates standard PCI type 0 and type 1 configuration access.
• High speed bus request and arbitration.
• Supports all PCI specific configuration registers.

Diagram

Description

The EP453 ARCtangent to PCI host bridge is a bus interface unit designed for efficient interface between the ARCtangent CPU and the PCI bus. This ARCtangent-PCI bridge IP core contains the functions of a bus master, bus target and the ability to initiate configuration access all in one core. It performs all the data transfer functions necessary for the bus mastering device to access data through the PCI bus. It supports burst data transfer to maximize data bandwidth. The target function allows other PCI masters to access internal system resources. It supports high speed bus request and arbitration to minimize transfer latency.

The ARCtangent to PCI host bridge operates in two clock domains, the CPU bus clock and the PCI bus clock. The two clock domain can be asynchronous to each other.

Single and burst data transfer are supported both as bus master and bus target. The interface to the internal controller is through a user-friendly local bus interface. It can be interfaced directly to the EP503 ARCtangent peripheral controller to provide access by the CPU core.

The ARCtangent-PCI bridge core allows the CPU to initialize the entire system during power-up reset using standard PCI protocol. Both type zero and type one transactions are supported. The CPU requests configuration access on the PCI bus by writing to or reading from the CONFIG_ADDR and CONFIG_DATA registers which are contained in the host bridge.

The ARCtangent to PCI host bridge initiates memory or IO read and write on the PCI bus. It contains 2 write buffers to post write data. Data can be written from the CPU side at the same time write operation is running on the PCI bus.

The ARCtangent to PCI host bridge functions as a PCI target when accessed by an external PCI bus master. The PCI target contains two write buffers and a read buffer to handle write posting and transfer data across the two clock domains. The request received from the PCI bus is forwarded upstream to internal system resources.