EP503 ARCtangent Peripheral Controller

Features

• Supports SDRAM, FLASH, PCI bridge and user defined slave devices.
• Interface to ARCtangent arbitration unit as a memory sequencer.
• Mapped to five separate address spaces: SDRAM, FLASH, PCI, control register and external slave device.
• Shares external address and data bus for all address spaces.
• Supports industrial standard 16Mbit, 64Mbit, 128Mbit and 256Mbit SDRAMs.
• Supports full page burst on SDRAM.
• Supports zero wait state burst data transfer to maximize data bandwidth.
• Programmable SDRAM and FLASH access timing parameters.
• Automatic SDRAM refresh generation with programmable refresh intervals.
• Multiple external SDRAM partitions.
• Byte collection and decomposition for narrow bus width FLASH devices.
• User-friendly interface to external slave devices.
• Programmable slave device access time.
• Interfaces directly with Eureka PCI host bridge.

Diagram

Description

The EP503 ARCtangent peripheral controller interfaces between the ARCtangent arbitration unit with SDRAM, FLASH, PCI host bridge, user defined slave devices and system control registers. It is optimized to serve as the slave device for the ARCtangent bus arbitration unit. Through the arbitration unit, request for the EP503 can originate from the CPU or any devices on the client interface of the arbitration unit.

SDRAM and FLASH timing such as row and column latency, precharge timing, and row access length are automatically handled by the memory controller. All these timing parameters are set by the memory controller on system reset and can be programmed by the user during run time to optimize system performance.

The ARCtangent peripheral controller supports all industrial standard SDRAM organizations, ranging from 16Mbit to 256Mbit devices, and from X4 data width to X16 data width. Data path width of the external memory system is 32-bit wide for the SDRAM and PCI and 16-bit wide for the FLASH.

Zero wait state data bursting is supported by the SDRAM controller and the PCI interface to maximize data throughput. Data bandwidth between the FLASH device is programmable through read/write access time parameters in the memory controller. Wait states can be inserted by the memory controller to match FLASH device speed.

Interface to user defined slave device is through a user-friendly interface from the EP503. Access timing to the slave device is programmable. Address and data bus can be shared among all memory and slave devices. The EP503 ARCtangent peripheral controller is designed to support external SDRAM and FLASH while the slave device and PCI host bridge can be either on-chip or off-chip.