AMBA AHB Bus Slave
- Supports AHB bus interface to the ARM CPU.
- User interface designed for high speed access to two sets of on-chip or off-chip modules.
- Four write buffers to process posted write.
- Dual read buffers to process CPU read.
- Read access to external bus handled as delay read to avoid system deadlock.
- Supports burst transfer and zero wait state to maximize data bandwidth.
- Supports data width of 8, 16 and 32 bits.
- Supports burst transfers up to 16 words of data.
- Supports early burst termination and CPU master busy.
- Multiple bus slave is supported by Ready signal input and outputs.
- Programmable address mapping to multiple address spaces.
- User interface optimized to access secondary bus such as PCI and memory subsystems based on SDRAM and FLASH.
- Optimized for ASIC and PLD implementations, including Excalibur PLD.