Product Summary  

 

 

EP454 AMBA AHB to PCI Host Bridge

Features

  • Fully supports PCI specification 2.2 to 3.0 protocol.
  • Supports AHB bus protocol, transfer size, burst size and response types.
  • Downstream access allows AHB bus devices such as CPU to access PCI bus.
  • Upstream access allows PCI bus devices to access system resources on AHB bus.
  • AHB bus and PCI bus operate at independent clock domains.
  • Total of six write buffers for write data posting for all interfaces.
  • Supports AHB burst transfers up to 16 data words.
  • Supports all AHB slave response types when functioning as AHB bus master.
  • PCI interface includes bus master, bus target and configuration access initiation.
  • Generates standard PCI type 0 and type 1 configuration accesses.
  • Read access to PCI bus handled as delay read to prevent system deadlock.
  • Automatic handling of configuration register read/write access.
  • Includes all PCI specific configuration registers.
  • User controlled base address register sizing and mapping.
  • Retry counter to limit bus access to non-responsive target device.
  • PCI status directly available to user logic for interrupt generation.
  • Optional features include Address Translation, DMA, PCI bus arbiter, Cardbus, PCMCIA, MiniPCI, Power management, and Hot swap.
  • Optimized for ASIC and PLD implementations, including on-chip ARM CPU.

Diagram

AMBA AHB to PCI host bridge