Product Summary  

 

 

EP454 AMBA AHB to PCI Host Bridge

Features

  • Fully supports PCI specification 2.2 to 3.0 protocol.
  • Supports AHB bus protocol, transfer size, burst size and response types.
  • Downstream access allows AHB bus devices such as CPU to access PCI bus.
  • Upstream access allows PCI bus devices to access system resources on AHB bus.
  • AHB bus and PCI bus operate at independent clock domains.
  • Total of six write buffers for write data posting for all interfaces.
  • Supports AHB burst transfers up to 16 data words.
  • Supports all AHB slave response types when functioning as AHB bus master.
  • PCI interface includes bus master, bus target and configuration access initiation.
  • Generates standard PCI type 0 and type 1 configuration accesses.
  • Read access to PCI bus handled as delay read to prevent system deadlock.
  • Automatic handling of configuration register read/write access.
  • Includes all PCI specific configuration registers.
  • User controlled base address register sizing and mapping.
  • Retry counter to limit bus access to non-responsive target device.
  • PCI status directly available to user logic for interrupt generation.
  • Optional features include Address Translation, DMA, PCI bus arbiter, Cardbus, PCMCIA, MiniPCI, Power management, and Hot swap.
  • Optimized for ASIC and PLD implementations, including on-chip ARM CPU.

Diagram

AMBA AHB to PCI host bridge

Description

The EP454 AMBA AHB to PCI host bridge is designed for interfacing the ARM CPU with the PCI bus and forward data access from both the upstream and downstream directions. The host bridge consists of three functional units: AHB bus slave, AHB bus master, and PCI interface. The AMBA AHB bus and the PCI bus can operate at two different clock domains.

Any bus mastering devices on the AMBA AHB bus can also access the host bridge. The core has multiple data buffers to achieve high speed data posting, prevent bus deadlock, and allow clock domain crossing for the data.

The AMBA AHB-PCI bridge core allows the ARM CPU to initialize the entire system during power-up reset using standard PCI protocol. Both type zero and type one transactions are supported. The CPU requests configuration access on the PCI bus by writing to or reading from the CONFIG_ADDR and CONFIG_DATA registers which are contained in the host bridge.

The AMBA AHB-PCI bridge initiates memory or IO read and write on the PCI bus upon AHB bus requests. It contains 4 write buffers, two in the AHB bus clock domain and two in the PCI clock domain, to post write data. Data can be written from the AMBA AHB bus at the same time write operation is running on the PCI bus.

Reading by the AMBA AHB bus is handled as delay read. The AHB slave retries the CPU while it is read data from the PCI bus. Instead of inserting wait state while waiting for return data, the AHB slave uses AHB bus retry to free up the AHB bus for other accesses. Once read data is read from the PCI bus, data returned to the CPU with zero wait state in subsequent read. The primary benefit of the delay read method is to prevent deadlock between the PCI bus and the AMBA AHB bus.

The AMBA AHB to PCI host bridge functions as a PCI target when accessed by an external PCI bus master. The PCI target contains two write buffers and a read buffer to handle write posting and transfer data across the two clock domains. The request received from the PCI bus is forwarded upstream to the AHB bus through the built-in AHB bus master. When function as a AHB bus master, the AMBA AHB to PCI host bridge supports all the bus slave response type, wait state insertion, and supports burst data transfer.