EP504 AMBA AHB Bus to SDRAM Controller

Features

• SDRAM controller interfaces directly with AHB Bus and user interface.
• Option for multiple access ports with built-in arbitration for memory sharing.
• Option to operate SDRAM and AHB bus at different bus frequency.
• Dual write buffer for simultaneous write posting and SDRAM access.
• Dedicated read buffer with data width matching.
• Early burst termination and CPU master busy on the AHB bus are supported.
• Supports AHB bus data width of 8, 16 and 32 bits.
• Zero wait state burst data transfer on both AHB interface and SDRAM.
• Supports industrial standard SDRAM from 64Mbit to 256Mbit device sizes.
• Pipeline access allows continuous data transfer without wasted cycle.
• Fast page access on row address matching.
• Independent row address matching for each of the 4 SDRAM banks.
• Programmable SDRAM access timing parameters.
• Automatic refresh generation with programmable refresh intervals.
• Option to support Mobile SDRAM.
• Optimized for ASIC and FPGA implementations.

Diagram

Description

The AHB bus SDRAM controller provides high speed SDRAM access for the system. It features one AHB port for user to access SDRAM. It is also available in multiple port configuration for memory sharing. All the access port can be AHB or a mixture of other bus interface. A generic user interface can be provided for optimal system core logic or DMA access. User interested in knowing how to configure a multiple port SDRAM controller design should read more about Eureka's MemConnect™ capability at http://www.eurekatech.com/products/memory/memconnect.htm.

The EP504 SDRAM controller contains built-in arbitration unit in the case of multiple port setup to allow both the AHB CPU and other system core logic to share SDRAM access. Sophiscated priority scheme allows data sharing to be customized to application requirements.

The SDRAM controller is a high performance SDRAM controller designed for transferring data to and from any industry standard SDRAMs or PC100/133 SDRAM DIMMs at the highest possible data rate.

The pipeline feature of the SDRAM controller allows the user port to specify the next access address while the current data transfer is in progress. Multiple data transfers can be cascaded together to read or write data from the SDRAM continuously, without any wasted cycle between accesses.

Another performance enhancement feature of the SDRAM controller is that it uses fast page access whenever there is a row hit. For each of the four internal banks, the SDRAM controller keeps the previous accessed row open. If the new request hits the same row, a column access is performed thus eliminate row access time. The SDRAM controller simultaneously keeps track of four open rows, one for each bank.

The SDRAM controller can be programmed to support different sizes and configurations of SDRAMs. The SDRAM device sizes supported are 64Mbits, 128Mbits, 256Mbits, and 512Mbits. The data width per SDRAM device can be programmed to 4, 8, 16 or 32 bits. The user can use single or multiple SDRAMs to build a 32-bit memory subsystems.

The SDRAM controller is fully programmable. All access timing parameters such as CAS latency, row-to-column delay, refresh interval, etc., are programmable to support different speed grades of SDRAM devices and different operating frequencies. All the timing parameters can be modified during run-time by a separate access port. The timing parameters can also be set to the proper default values during compile time so that there is no need to program them during run-time.

The user interface of the SDRAM controller is a user-friendly synchronous bus, similar to the I960 microprocessor interface. The user provides the address for each access and the SDRAM controller automatically generate the row (RAS) and column (CAS) access cycles to transfer data. The user can specify single or burst data transfer. In burst data transfer, zero wait state data bursting is supported to maximize memory bandwidth. SDRAM refresh cycle is periodically issued by the SDRAM controller. The refresh cycles are transparent to the AHB bus or the user interface.

Optional Features

The EP504 can be available as a very simple SDRAM controller or can be customized to support many advanced features. The following is a list of the most popular optional features. These features need to be specified when ordering the IP core.