AMBA AHB Bus to SDRAM Controller
- SDRAM controller interfaces directly with AHB Bus and user interface.
- Dual write buffer for simultaneous write posting and SDRAM access.
- Dedicated read buffer with data width matching.
- Early burst termination and CPU master busy on the AHB bus are supported.
- Supports AHB bus data width of 8, 16 and 32 bits.
- Zero wait state burst data transfer on both AHB interface and SDRAM.
- Supports industrial standard SDRAM from 64Mbit to 256Mbit device sizes.
- Pipeline access allows continuous data transfer without wasted cycle.
- Fast page access on row address matching.
- Independent row address matching for each of the 4 SDRAM banks.
- Programmable SDRAM access timing parameters.
- Automatic refresh generation with programmable refresh intervals.
- Optimized for ASIC and FPGA implementations.
- Multi port input.
- Mobile DDR.
- Multiple clock domain for user ports.
- Multiple SoC and FPGA standard bus interface support (e.g. AHB-Lite, Avalon, PowerPc, Wishbone, SH4).
- Different data with matching.