Memory Controllers  

 

 

Our memory controllers are

enabled with a variety of

powerful features.

NAND Flash FAQWhite paper : Understanding NAND Flash

Synchronous NAND Flash Controller IPNAND Flash Controller, ONFI Synchronous

NAND Flash Controller IPNAND Flash Controller, Asynchronous

NOR Flash/ROM/SRAM Controller IPNOR Flash/ROM/SRAM

MemConnectMemConnect

DDR3 SDRAM Controller

DDR2 SDRAM Controller

DDR SDRAM Controller IPDDR SDRAM Controller

SDRAM Controller IPSDRAM Controller

AMBA AHB-SDRAM ControllerAHB to SDRAM Controller

AMBA AHB-DDR SDRAM ControllerAHB to DDR SDRAM Controller

Controller


White paper : NAND Flash FAQ
Check out questions that are frequently asked about NAND Flash, from what it is to how it works; ECC, bad block management, wear leveling, etc.

 

Synchronous ONFI NAND Flash Controller
The EP502 Synchronous NAND Flash controller provides an easy interface for user to access single-level and multi-level cell (SLC and MLC) synchronous and asynchronous NAND Flash devices. NAND Flash devices are normally accessed through a complicated sequence of command, address, data, and confirmation protocols. The EP502 manages all the hardware protocols and allows the user to access NAND Flash memory simply by reading and writing the register set of the IP core.

 

Asynchronous NAND Flash Controller
The EP501 NAND Flash controller provides an easy interface for user to access NAND Flash devices simply by reading and writing control registers inside the EP501. It supports optional error correction code (ECC) that performs single-bit error correction and double-bit error detection.

 

NOR Flash/ROM/SRAM Controller
The EP500 Flash/ROM/SRAM controller core allows two or more access ports to share memory access to the FLASH, ROM and SRAM devices. The core automatically arbitrates between the two access ports so each can access memory independently.

 

MemConnect
MemConnect™ is a comprehensive, customizable, and silicon proven IP solution for memory system design. It supports any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, ROM, SRAM and NAND Flash, all in one IP core. A complete line of user interfaces including AMBA AHB, AXI, MIPS SysAD and EC interface, PowerPC, PCI, PCI-X, PCI Express, a built-in DMA controller, as well as a high performance simple user interfaces for shared memory access within an SOC design are supported.

 

DDR3 SDRAM Controller
The EP538 DDR SDRAM controller supports both DDR2 and DDR3 SDRAM devices. It is an interface between multiple DDR2 or DDR3 SDRAM devices and its memory requestor such as processor or DMA controller.

 

DDR2 SDRAM Controller
The EP532 DDR2 SDRAM controller interfaces between DDR/DDR2 SDRAM and user logic. It supports all industrial standard DDR/DDR2 SDRAM, ranging from 64Mbit to 2 Gigabit devices, and from X4 data width to X16 data width.

 

DDR SDRAM Controller
The EP530 DDR SDRAM controller interfaces between DDR SDRAM and user logic. It supports all industrial standard SDRAM organizations, ranging from 64Mbit to 256Mbit devices, and from X4 data width to X32 data width.

 

Pipeline SDRAM Controller
The EP525 pipeline SDRAM controller is a high performance SDRAM controller designed for transferring data to and from any industry standard SDRAMs or PC100/133 SDRAM DIMMs at the highest possible data rate. It supports column-only access in during page hit and pipeline access to overlap address and data transfer.

 

AHB to SDRAM Controller
This controller provides high speed SDRAM data access to the ARM CPU and user-defined logic. Two port architecture provides sharing of memory without consuming data bandwidth on the AMBA AHB bus.
  • Provides direct access from AHB bus to standard SDRAM devices.
  • Shared memory between AHB bus and user-defined logics.
  • Programmable SDRAM architecture and timing parameters.
  • Fast page access on page hit.
  • Pipeline access by user port to maximize bandwidth.

 

AHB to DDR SDRAM Controller
This controller provides high speed DDR SDRAM data access to the ARM CPU and user-defined logic. Two port architecture provides sharing of memory without consuming data bandwidth on the AMBA AHB bus.
  • Operates on both discrete DDR SDRAM chips and DDR SDRAM DIMM.
  • External pin reduction by transferring two bits of data per pin.
  • Programmable memory size and timing parameters.