MemConnect
MemConnect™ is a comprehensive, customizable, and silicon proven IP solution for memory
system design. It supports any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM,
Flash, ROM, SRAM and NAND Flash, all in one IP core. A complete line of user interfaces
including AMBA AHB, AXI, MIPS SysAD and EC interface, PowerPC, PCI, PCI-X, PCI Express,
a built-in DMA controller, as well as a high performance simple user interfaces for shared memory
access within an SOC design are supported.
Pipeline SDRAM Controller
The EP525 pipeline SDRAM controller is a high performance SDRAM
controller designed for transferring data to and from any industry
standard SDRAMs or PC100/133 SDRAM DIMMs at the highest possible
data rate. It supports column-only access in during page hit
and pipeline access to overlap address and data transfer.
DDR SDRAM Controller
The EP530 DDR SDRAM controller interfaces between DDR SDRAM and user logic.
It supports all industrial standard SDRAM organizations, ranging from 64Mbit to 256Mbit
devices, and from X4 data width to X32 data width.
DDR2 SDRAM Controller
The EP532 DDR2 SDRAM controller interfaces between DDR/DDR2 SDRAM and user logic.
It supports all industrial standard DDR/DDR2 SDRAM, ranging from 64Mbit to 2 Gigabit
devices, and from X4 data width to X16 data width.
AHB to SDRAM Controller
This controller provides high speed SDRAM data access to the ARM CPU and user-defined logic.
Two port architecture provides sharing of memory without consuming data bandwidth on the
AMBA AHB bus.
- Provides direct access from AHB bus to standard SDRAM devices.
- Shared memory between AHB bus and user-defined logics.
- Programmable SDRAM architecture and timing parameters.
- Fast page access on page hit.
- Pipeline access by user port to maximize bandwidth.
AHB to DDR SDRAM Controller
This controller provides high speed DDR SDRAM data access to the ARM CPU and user-defined logic.
Two port architecture provides sharing of memory without consuming data bandwidth on the
AMBA AHB bus.
- Operates on both discrete DDR SDRAM chips and DDR SDRAM DIMM.
- External pin reduction by transferring two bits of data per pin.
- Programmable memory size and timing parameters.
NAND Flash Controller
The EP501 NAND Flash controller provides an easy interface for user to access NAND Flash devices
simply by reading and writing control registers inside the EP501. It supports optional error correction
code (ECC) that performs single-bit error correction and double-bit error detection.
NAND Flash Frequently Asked Questions
Check out questions that are frequently asked about NAND Flash, from what it is to what it does;
bad blocks and ECC etc.
Flash/ROM/SRAM Controller
The EP500 Flash/ROM/SRAM controller core allows two or more access ports to share memory access
to the FLASH, ROM and SRAM devices. The core automatically arbitrates between the two access ports
so each can access memory independently.
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MemConnect