EP500 Flash/ROM/SRAM Controller

Features

• Supports industry standard Asynchronous SRAM, NOR Flash, ROM and similar memory devices.
• Two request ports to allow two requesters to share access to the FLASH/ROM/SRAM devices.
• 8 Chip select signals to access up to 8 memory banks.
• Independent programmable timing parameters for each chip select.
• Independent address mapping for each chip select.
• Independent programmable data width of 8, 16 and 32 bits for each chip select.
• Supports 32-bit and 64-bit user interface bus width.
• Supports burst access from the request ports.
• Automatic issues multiple access to memory device (byte collection) to match data word size of memory device with user interface data width.
• Optional AHB user interface.
• Optional ECC protection.
• Optimzed for logic synthesis for ASIC and FPGA implementations.
• Fully static design with edge triggered flip-flops.

Diagram

Description

The EP500 Flash/ROM/SRAM controller core allows two or more access ports to share memory access to the FLASH, ROM and SRAM devices. The core automatically arbitrates between the two access ports so each can access memory independently. Multiple memory devices can be accessed by the controller with different chip select signals. The address depth of each chip select signal is programmable by the user.

The user interface can be selected to 64 or 32-bit wide. The memory interface can be 8, 16 or 32-bit wide. If the memory interface is narrower than the user interface, the core automatically compose or decompose data (byte collection) to match data word size of memory device with user interface data width. The core also support burst access by the user. It handles burst access by issuing multiple access to the FLASH, ROM or SRAM devices.

The FLASH/ROM/SRAM memory devices are asynchronous devices which do not use the clock input. The controller core generates timing control signals to all these devices base on input clock signal. Access timing parameters are programmable by the user through control registers built-in to the core.

Optional error correction code (ECC) is supported by the core and the core can be designed to share address and/or data bus with other devices such as SDRAM.