Product Summary  



download NAND Flash Controller informationEP501 NAND Flash Controller

Frequently Asked Questions about NAND Flash


  • Supports single-level and multi-level cells (SLC and MLC) NAND Flash devices.
  • Available EP502 NAND Flash controller for synchronous NAND support.
  • ECC correction with BCH code for up to 60-bit ECC error per 512 or 1k byte of data blocks.
  • Optional no ECC or 1-bit ECC support with Hamming code.
  • Programmable support for different page and spare column sizes.
  • Simple user interface designed for easy on-chip integration.
  • Choices of AHB, AXI, Wishbone, PLB and Avalon user interface.
  • Large Flash memory space can be accessed through data register mapping.
  • Programmable access timing.
  • ONFI NAND compliant with support for non-standard commands.
  • User has full access to spare data in NAND Flash device.
  • Support boot-from-NAND with or without DMA.
  • Optional built-in DMA engine for autonomous data transfer.
  • Optional support for 16-bit wide NAND Flash device.
  • Write-triggered read operation eliminate long wait state when open new pages.
  • Supports two-plane page program and erase for improved system bandwidth.
  • Compatible with standard FTL and Linux JFFS2 for wear leveling and bad block management.
  • Optimized for ASIC and FPGA implementations.

Differentiating Features

  • Choices of AHB, AXI, PLB, Wishbone and Avalon user interface.
  • Hamming code and BCH ECC.
  • Built in DMA Controller for boot code and data transfer.
  • 16 bit NAND Flash data width.


NAND Flash Controller IP core block diagram