EP501 NAND Flash Controller

Frequently Asked Questions about NAND Flash

Features

• Supports single-level and multi-level cells (SLC and MLC) NAND Flash devices.
• Supports 1, 4 and 8 bit ECC correction per 512byte.
• Uses Hamming code for SLC and BCH code for multi-bit correction in MLC.
• Programmable support for large block and small block NAND Flash devices with 512, 2k and 4k byte page sizes.
• Simple user interface designed for easy on-chip integration.
• Choices of AHB, AXI, Wishbone and Avalon user interface.
• Large Flash memory space can be accessed using data and index register method.
• Programmable access timing.
• Configurable number of banks and devices per bank.
• Supports ONFI standard command interface.
• User has full access to spare data in NAND Flash device.
• Write-triggered read operation eliminate long wait state when open new page for read.
• Enable NAND flash be used as Boot ROM by automatic page open and DMA.
• Supports two-plane page program and erase for doubling system bandwidth.
• Compatible with standard FTL and Linux JFFS2 for wear leveling and bad block management. Low level drivers available.
• Option to transfer data with NAND Flash through DMA.
• Designed for ASIC and FPGA implementations.

Differentiating Features

• Choices of AHB, AXI, PLB, Wishbone and Avalon user interface.
• Hamming code and BCH ECC.
• Built in DMA Controller for boot code and data transfer.

Diagram