Synchronous ONFI NAND Flash Controller
Frequently Asked Questions about NAND Flash
- Supports single-level and multi-level cells (SLC and MLC) NAND Flash devices.
- Compatible with ONFI Flash Interface for synchronous and asynchronous access.
- Supports source synchronous double data rate data transfer for highest possible data bandwidth.
- Supports different page and spare column sizes.
- Simple user interface designed for easy on-chip integration.
- Choices of AHB, AXI, Wishbone and Avalon user interface.
- Built-in DMA engine for autonomous data transfer.
- Internal data buffer to maximize data bandwidth.
- ECC correction with BCH code for up to 60-bit ECC error per 512 or 1k byte data blocks.
- Options for hardware or software error correction to optimize size and performance.
- Stores ECC code in spare column area with programmable size for user access.
- Write-triggered read operation eliminates long wait states when open a new page,
- Supports boot-from-NAND Flash with and without DMA.
- Compatible with standard FTL software and Linux JFFS2 for wear leveling and bad block management.
- Designed for ASIC and FPGA implementation
- Choices of AHB, AXI, PLB, Wishbone and Avalon user interface.
- hardware or software error correction.
- Built in DMA Controller for boot code and data transfer.