Product Summary  



download Synchronous NAND Flash Controller informationEP502 Synchronous ONFI NAND Flash Controller

Frequently Asked Questions about NAND Flash


  • Supports single-level and multi-level cells (SLC and MLC) NAND Flash devices.
  • Compatible with ONFI 2.1 Flash Interface for synchronous and asynchronous access.
  • Supports source synchronous double data rate data transfer for highest possible data bandwidth.
  • Supports 2k and 4k page sizes.
  • Simple user interface designed for easy on-chip integration.
  • Choices of AHB, AXI, Wishbone and Avalon user interface.
  • Built-in DMA engine for autonomous data transfer.
  • Internal data buffer to maximize data bandwidth.
  • Optional ECC correction with BCH code for 4, 8, 12 or more error bits per 512 bytes.
  • Stores ECC code in spare column area.
  • Write-triggered read operation eliminates long wait states when open a new page,
  • Enable NAND Flash to be used as BOOT ROM.
  • Compatible with standard FTL software and Linux JFFS2 for wear leveling and bad block management.
  • Designed for ASIC and FPGA implementation

Differentiating Features

  • Choices of AHB, AXI, PLB, Wishbone and Avalon user interface.
  • Hamming code and BCH ECC.
  • Built in DMA Controller for boot code and data transfer.


Syncrhonous NAND Flash Controller IP core block diagram