EP525 Pipeline SDRAM Controller

Features

• Designed with synthesizable HDL for ASIC and PLD synthesis.
• Supports both discrete SDRAM chips and PC100/133 SDRAM DIMM.
• Supports register mode and non-register mode SDRAM DIMM.
• Supports industrial standard SDRAM from 64Mbit to 512Mbit device sizes.
• Page hit detection to support multiple column accesses within the same row.
• Pipeline access allows continuous data bursting.
• Programmable memory size: 4, 8, 16 and 32 bits per SDRAM.
• Programmable word size:16, 32 and 64 bits.
• Supports all burst lengths: 1, 2, 4, 8 and full page.
• Zero wait state burst data transfer.
• Programmable SDRAM access timing parameters.
• Supports multiple external SDRAM banks.
• Automatic refresh generation with programmable refresh intervals.
• Programmable memory configuration registers.

Diagram

Description

The EP525 SDRAM Controller is an interface between multiple SDRAM memory storage and a processor or DMA device. It performs SDRAM read and write accesses based on the processor or DMA requests.

The SDRAM timing, such as row and column latency, precharge timing, and row access length, are programmed to their default values at system reset. They can also be reprogrammed during run time if the user wishes to change them to optimize system performance. The internal counters in the SDRAM controller handle all the timing parameters.

This design supports SDRAM sizes of 64, 128, 256 and 512Mbits. For the 64Mbit and 128Mbit SDRAMs, it supports the configurations of x4, x8, x16, and x32 data width per SDRAM device, and for the 256Mbit and 512Mbit SDRAMs, it supports the configurations of x4, x8, and x16 data width per SDRAM device. The user can use multiple SDRAMs to build a word size from 16 bits to 64 bits, or use standard SDRAM DIMMs to build the memory system. Both device size and word size are programmable by the user.

Zero wait state data bursting is supported by the SDRAM controller to maximize data throughput. The user interface to user device such as CPU or DMA controller is a standard microprocessor bus with wait state control. It can be optimized easily to meet different application requirements.

The EP525 SDRAM Controller also supports page mode access. The page mode access takes advantage of the fact that once a row is activated, multiple accesses can be made to the same row (page) without precharging the bank. The SDRAM controller does not issue any precharge command until a specific precharge request is given by the user.

Another feature of this design, the pipeline feature, allows the user to request the next access while the current access is being processed. This allows the SDRAM controller to issue consecutive page hit read or consecutive page hit write to SDRAM without any idle cycles between accesses.

Optional Features

The EP525 SDRAM controller supports the following optional features per customer specification.