Product Summary  



download SDRAM controller informationEP525 Pipeline SDRAM Controller


  • Designed with synthesizable HDL for ASIC and PLD synthesis.
  • Supports both discrete SDRAM chips and PC100/133 SDRAM DIMM.
  • Supports register mode and non-register mode SDRAM DIMM.
  • Supports industrial standard SDRAM from 64Mbit to 512Mbit device sizes.
  • Page hit detection to support multiple column accesses within the same row.
  • Pipeline access allows continuous data bursting.
  • Programmable memory size: 4, 8, 16 and 32 bits per SDRAM.
  • Programmable word size:16, 32 and 64 bits.
  • Supports all burst lengths: 1, 2, 4, 8 and full page.
  • Zero wait state burst data transfer.
  • Programmable SDRAM access timing parameters.
  • Supports multiple external SDRAM banks.
  • Automatic refresh generation with programmable refresh intervals.
  • Programmable memory configuration registers.

Differentiating Features

  • Power saving mode.
  • ECC or parity support.


block diagram of SDRAM controller