EP530 DDR SDRAM Controller

Features

• Supports industry standard Double Data Rate (DDR) SDRAM from 64Mbit to 512Mbit device sizes.
• Page hit detection to support multiple column accesses within the same row.
• Pipeline access allows continuous data bursting.
• External pin reduction by transferring 2 bits of data per pin.
• Provide user data at twice the data width compared to DDR SDRAM data.
• Programmable SDRAM data width and user word size.
• Supports burst lengths of 2, 4 and 8 words.
• Programmable SDRAM access timing parameters.
• Supports multiple external SDRAM banks.
• Automatic refresh generation with programmable refresh intervals.
• Self-refresh mode to reduce system power consumption.
• Programmable memory configuration registers.
• Integrated data buffer synchronizes user interface with DDR SDRAM data.
• Designed with synthesizable HDL for ASIC and FPGA synthesis.

Diagram

Description

The EP530 DDR SDRAM Controller is an IP core that interface between multiple DDR SDRAM devices and a memory requestor such as a processor or DMA device. It performs DDR SDRAM read and write accesses based on the processor or DMA requests.

The SDRAM timing, such as row and column latency, precharge timing, and row access length, are programmed to their default values at system reset. They can also be reprogrammed during run time if the user wishes to change them to optimize system performance. The internal counters in the DDR controller handle all the timing parameters.

Data between the DDR core and the DDR SDRAM is transferred at both the rising edge and falling edge of the clock input. This creates very tight timing requirement for generating write data and sampling read data. The DDR controller core has a built-in data path that handles all the data generation and sampling tasks. For read access, data is sampled by the data path and the double data rate. Data is then synchronized with the internal clock and transferred to the user interface one-word per clock cycle as normal data. For write access, data is received from the user interface at the normal one-word per clock data rate. The DDR controller's data path then resynchronizes the data and transfers them using the double data rate.

The EP530 DDR SDRAM controller supports SDRAM sizes of 64, 128, 256 and 512Mbits. For the 64Mbit and 128Mbit SDRAMs, it supports the configurations of x4, x8, x16, and x32 data width per SDRAM device, and for the 256Mbit and 512Mbit SDRAMs, it supports the configurations of x4, x8, and x16 data width per SDRAM device. The user can use multiple SDRAMs to build a word size from 32 bits to 128 bits, or use standard SDRAM DIMMs to build the memory system. Both device size and word size are programmable by the user.

The EP530 DDR SDRAM core supports page mode access. The page mode access takes advantage of the fact that once a row is activated, multiple accesses can be made to the same row (page) without precharging the bank. The DDR controller does not issue any precharge command until a specific precharge request is given by the user.

Another feature of the SDRAM DDR controller is the pipeline feature, allows the user to request the next access while the current access is being processed. This allows the SDRAM DDR controller to issue consecutive page hit read or consecutive page hit write to SDRAM without any idle cycles between accesses.