EP532 DDR2 SDRAM Controller

Features

• Supports industry standard Double Data Rate (DDR) and Double Date Rate2 (DDR2) SDRAM from 64Mbit to 2Gbit device sizes.
• Issue precharge, active and read/write commands to a different banks and keeps multiple banks active at the same time.
• Integrated data buffer (Soft PHY) captures and synchronizes SDRAM data using programmable delay cells or DLL.
• Supports bulit-in soft DDR PHY or external hard PHY such as DFI.
• User controlled variable additive latency for DDR2 device.
• On-die termination (ODT) support optimized for single and multiple SDRAM DIMM.
• Off-Chip Driver impedance adjustment (OCD) support for DDR2 devices.
• Programmable SDRAM access timing parameters and configurations.
• Automatic refresh generation with programmable refresh intervals.
• Self-refresh mode to reduce system power consumption.

Differentiating Features

• Multi port input.
• Mobile DDR.
• Multiple clock domain for user ports.
• Multiple SoC and FPGA standard bus interface support (e.g. AHB, Avalon, PowerPC, Wishbone, SH4).

Diagram