EP532 DDR2 SDRAM Controller

Features

• Supports industrial standard Double Data Rate (DDR) and Double Date Rate2 (DDR2) SDRAM from 64Mbit to 2Gbit device sizes.
• Page hit detection to support multiple column accesses within the same row.
• Pipeline access allows continuous data bursting and hidden active commands, even with page misses.
• Issue precharge, active and read/write commands to a different banks and keeps multiple banks active at the same time.
• Integrated data buffer (Soft PHY) captures and synchronizes SDRAM data using programmable delay cells or DLL.
• Supports bulit-in soft DDR PHY or external hard PHY such as DFI.
• User controlled variable additive latency for DDR2 device.
• On-die termination (ODT) support optimized for single and multiple SDRAM DIMM.
• Off-Chip Driver impedance adjustment (OCD) support for DDR2 devices.
• Programmable SDRAM access timing parameters and configurations.
• Automatic refresh generation with programmable refresh intervals.
• Self-refresh mode to reduce system power consumption.
• Numerous optional features such as multiple access ports, user interface, ECC, Mobile SDRAM supports and others.

Diagram

Description

The EP532 DDR2 SDRAM Controller is an IP core that supports both DDR and DDR2 SDRAM devices. It is an interface between multiple DDR or DDR2 SDRAM devices and a memory requestor such as a processor or DMA device. The DDDR / DDR2 Controller allows the user logic to simply reads from or writes to the memory system without having to be concerned about specific SDRAM control and timing issues. The DDR / DDR2 Controller presents the simple and efficient protocol to the user for both DDR and DDR2, while hiding the complicated SDRAM behavior and taking advantage of the access characteristics of DDR and DDR2 SDRAMs to sustain high bandwidth.

Data between the DDR / DDR2 controller core and the DDR / DDR2 SDRAM is transferred at both the rising edge and falling edge of the clock input. This creates very tight timing requirements for generating write data, as well as for sampling read data. The DDR / DDR2 controller core has a built-in data path that handles all data generating and sampling tasks. For read accesses, data is sampled by the data path at the double data rate. Data is then synchronized with the internal clock and transferred to the user interface one-word per internal clock cycle. For write accesses, data is received from the user interface at the normal one-word per internal clock data rate. The DDR / DDR2 controller’s data path then re-synchronize the data and transfers them using the double data rate. The DDR / DDR2 controller has several data path designs for different requirements. The core uses fixed or programmable delay cells for the alignment of SDRAM data. The use of a user provided DLL delay element is optional.

High performance and high data bandwidth are essential to any SDRAM controller design. The EP532 DDR / DDR2 SDRAM controller has two main features designed to extract the highest performance and data bandwidth possible from the SDRAM device.

The first feature is fast page mode access, or CAS only access. The EP532 DDR / DDR2 SDRAM controller automatically keeps each bank open after previous accesses and maintains a record of the open row addresses. It compares incoming requests with the existing row address for each bank. If the new request is to an open row (a page hit), the DDR / DDR2 controller issues a CAS only access to speed up data transfer.

The second feature is pipeline access. It allows the user to request the next access while the current access is being processed. This allows the DDR / DDR2 controller to issue precharge, active and read/write commands for the next transfer during the current data access. With pipeline access, the DDR / DDR2 SDRAM controller can continuously support data bursting without any idle cycles, even in the event of continuous page misses.

The SDRAM timing, such as row and column latency, precharge timing, and row access length, are programmed to their default values at system reset. They can also be reprogrammed during run time if the user wishes to change them to optimize system performance. The internal counters in the controller core handle all the timing parameters.

DDR and DDR2 support is programmable through the control registers inside the core. For DDR2 applications, the core supports many DDR2 specific features such as additive latency, Qoff, Off-chip driver calibration (OCD) and On-die termination (ODT). ODT support is optimized for single or multiple termination of the data path. The EP532 DDR / DDR2 controller supports single and dual SDRAM DIMM slots.

In DDR2 applications, the core supports 256Mbit, 512Mbit, 1Gbit and 2Gbit SDRAM devices. For DDR application, the core supports SDRAM sizes of 64Mbit, 128Mbit, 256Mbit, 512Mbit, and 1Gbit devices. The core supports configurations of x4, x8, and x16 data width per SDRAM device. The user can either use multiple SDRAMs to build user word size from 32 bits to 128 bits, or use standard SDRAM DIMMs to build their memory systems. Both the device size and word size are user programmable. Up to 16 Gbytes of memory can be controlled by the EP532 SDRAM controller.

Control and address signal can be connected directly to the processor and the SDRAM controller or through off-chip registers such as register mode in SDRAM DIMMs.

The EP532 has optional error correction code (ECC) support for single bit error correction and double bit error detection. Eight check bits are generated for each 64 bits of data. When ECC is used, the EP532 generates read-modify-write cycles if a partial word is written to SDRAM.

Optional Features

The EP532 can be available as a very simple SDRAM controller or can be customized to support many advanced features. The following is a list of the most popular optional features. These features need to be specified when ordering the IP core