Some reference designs which show how MemConnect can be configured are shown below:
Example 1: A Simple DDR2 Controller
The first example above shows a simple DDR2 design. There is only one memory device in this configuration,
a DDR2 SDRAM running at 200 Mhz. It is connected to both an AMBA AHB bus interface, as well as a simple user
interface. Since there are multiple interfaces, an arbiter is required. This arbiter can have any one of various arbitration
Example 2: A Dual Memory System
The second example above shows a slightly more complicated scenario. There are two memory devices, Flash
and SDR SDRAM. The two memories each have their own memory controller. Note that the two memories have a
shared data bus, which is an option configurable in MemDesigner. This has the benefit of reducing the number of pins
required. It also creates a wider bus to the Flash memory than in a typical configuration. The disadvantage is that
simultaneous access to both the Flash and the SDR SDRAM is not possible. Depending on the application this may
or may not be acceptable. MemDesigner allows you to customize the system to your needs
The SDR controller utilizes the optional Error Correction Code. The memory devices are connected to 3 bus
interfaces, a MIPS bus, a simple user interface, and an AMBA AHB bus. These buses can then be connected as the
user desires. The arbiter in this second example is a little bit more complicated than in the first example, handling
3 different interfaces rather than 2 is used here.
Example 3: A Complex Memory System
The example above has four different types of memories: NAND Flash, SRAM, Flash, and DDR SDRAM. The
SRAM and Flash share a memory controller and have a shared data bus as well. Alternatively, they could have had
separate controller to allow for concurrent access. Note that both the memories and the interface buses all have different
data widths, which is fully supported with MemConnect.
The PCI Bus interface in this example demonstrates the ability of MemConnect to operate across different clock
domains. The PCI has direct and exclusive access to the NAND Flash, and shares access to the SRAM/Flash with
the PowerPC bus. The optional DMA controller is used in this example, and is connected to the DDR SDRAM, along
with the other 2 interfaces.
Ready to design your system ?
MemConnect encapsulate many years of design expertise through our engagement with different customers and
various requirements. We may not have seen it all but we have seen a wide variety of memory system designs. Our
accumulated knowledge of the area of memory system design is carefully preserved in the MemConnect IP. The
MemDesigner software will guide you through the design process. The previous examples merely presented a few
snapshots of what MemConnect is capable of. Leverage our expertise at putting cores together to come up with the
ideal solution for your needs !
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