EP150 MIPS SysAD Bus Slave

Features

• Supports 64-bit MIPs CPU bus through the SysAD bus interface.
• Supports single and burst access from CPU.
• Dispatches CPU request to SDRAM controller, FLASH controller, PCI, user interface, and system control registers.
• Supports two outstanding read operation to two groups of data sources.
• Supports out-of-order data return.
• Two write buffers to maximize data bandwidth.
• Centralized control of all access to system control registers by CPU and by user logic.
• Provide access path from CPU to external user logic.
• All input signals from CPU are sampled by flip-flops before propagate to other logic in order to minimized input setup time.
• Address translation between the SysAD bus address space and the PCI address space.
• Boot-mode initialization serial bit stream and CPU reset generation.

Diagram

Description

The EP150 is an SysAD bus slave device designed to interface various user logic with the MIPS CPU through the SysAD bus. It decodes the CPU address and dispatches the request to user logic through two user interface ports. The bus slave also regulates the data flow between all ports to optimize performance. Different user logic such as SDRAM controller, FLASH controller, PCI host bridge, DMA and UART can be connected to the SysAD bus through the slave.

The EP150 SysAD bus slave interfaces with the MIPS CPU to receive access request and dispatch them to the internal blocks of the bus slave. Request can be dispatched to the following areas: (1) SDRAM, (2) FLASH boot ROM, (3) PCI bus and PCI registers, (4) three sets of external control registers, and (5) I/O port D.

There are internal control registers residing within the EP150. Access to these registers are processed by the EP150 and not dispatched outside.

The EP150 is capable of simultaneously transferring data between the SysAD bus interface and the two user interfaces. Both user interface ports can be transferring data simultaneously. Both user interface ports use a very simple and user-friendly protocol so that different types of user logic other than PCI and memory controller can be connected to either interface ports.

The SysAD bus slave contains two write buffers that can be shared by both user interfaces. Each write buffer can store up to 32 bytes of data. The dual write buffer structure allows the CPU to post write data into one buffer while the user interface is extracting data from the write buffer.

Reading by the SysAD bus can be issued to both interfaces at the same time Once read data is available from the user interface, it is returned to the CPU immediately. Zero wait state data bursting is allowed to maximize data bandwidth.

The SysAD bus slave also supports out-of-order read when reading from both user interface ports. The first data returned from one user interface is transferred to the CPU while data from the second user interface is buffered in the internal read buffer and transferred after the first set of read data.