EP155 MIPS EC Interface Bus Slave

Features

• Designed with synthesizable HDL for ASIC and FPGA synthesis.
• Compliant to the EC Interface of the MIPS CPU.
• Supports MIPS64 5K and MIPS32 4K processor core family.
• Supports separate address and data phases on the EC bus interface.
• Dual write buffers to support write posting.
• Up to 3 bus transfers outstanding at various stage of processing.
• Supports address pipeline by EC interface.
• Out of order access completion and separate read and write data phase.
• Supports both single and burst transfer.
• Sequential ordering burst address sequence.
• Supports any number of wait states in address and data phases.
• Multiple user logics such as the SDRAM controller, PCI host bridge and system control registers can be access through the bus slave.
• Supports parallel write to two different agents at the backend to improve the system performance.
• Address translation between the EC bus address space and the PCI address space.

Diagram

Description

The EP155 EC Interface bus slave controller is compliant to the EC interface specification and is designed as a slave to interface to all MIPS64 5K and MIPS32 4K processor cores. The EC bus slave can be synthesized into ASIC or FPGA and with its expandable backend interface, the slave can be connected to many other Eureka cores such as the SDRAM controller and PCI host bridge. The EC bus slave can also be used to access the system control registers and interface to the user logic.

The EC interface bus slave supports 64-bits data bus width with separate read and write data buses and separate read and write bus error indications on the EC bus interface. All signals are unidirectional and all signals to the master are registered. It has separate address and data phases which allows address pipelining on the EC bus interface. This EC interface IP supports both single and burst transfer with sequential ordering burst address sequence. Both back-to-back read transactions and back-to-back write transactions are also supported. There is no limit on the number of wait states in address and data phases.

The EC bus slave is capable of simultaneously transferring data between the EC interface and the two user interfaces. One user interface is optimized for memory controller access and the other user interface is optimized for peripheral bus controller access such as PCI bus access. However, both user interface ports use a very simple and user-friendly protocol so that different types of user logic other than PCI and memory controller can be connected to either interface ports.

Up to three different accesses can be processed by the EC bus slave at the same time. The bus slave implements two write buffers for write posting. The write buffers are shared among the user interfaces to maximize the EC bus efficiency and system performance. The slave can transfer write data at both user interface simultaneously. The bus slave provides address translation when interface with external bus such as PCI bus. Translation control registers are built-in to the slave.

All output signals to the processor core, including the read data, are registered before going out to the EC bus.