Product Summary  

 

 

EP455 EC Interface to PCI Host Bridge

Features

  • Fully supports PCI specification 2.1 and 2.2 protocol.
  • Supports MIPS EC Interface bus protocol.
  • Downstream access transfer from MIPS EC Interface bus to PCI bus.
  • Upstream access transfer from PCI bus to internal system resources.
  • EC Interface bus and PCI bus operate at independent clock domains.
  • Total of six write buffers for data write posting for all interfaces.
  • Supports EC Interface burst transfers up to 64 bytes.
  • PCI interface includes bus master, bus target and configuration access initiation.
  • Generates standard PCI type 0 and type 1 configuration accesses.
  • Automatic handling of configuration register read/write access.
  • Supports target retry, disconnect, abort and wait state insertion.
  • Parity generation and parity error detection.
  • Includes all PCI specific configuration registers.
  • Supports high speed bus request and bus parking.
  • Optional PCI bus arbiter with fix, rotating, and custom priority.

Diagram

Description

The EP455 PCI host bridge is designed for interfacing a MIPS CPU on EC Interface with the PCI bus and forwarding data access from both the upstream and downstream directions. The host bridge consists of three functional units: EC Interface bus slave, PCI interface, and optionally, a PCI bus arbiter. The EC Interface bus and the PCI bus can operate at two different clock domains.

The EC Interface-PCI bridge core has multiple data buffers to achieve high speed data posting, prevent bus deadlock, and allow clock domain crossing for the data.

The EC Interface to PCI host bridge core allows the CPU to initialize the entire system during power-up reset using standard PCI protocol. Both type zero and type one transactions are supported. The CPU requests configuration access on the PCI bus by writing to or reading from the CONFIG_ADDR and CONFIG_DATA registers which are contained in the host bridge.

The EC Interface to PCI host bridge initiates memory or IO read and write on the PCI bus upon EC Interface bus requests. It contains 4 write buffers, two in the EC Interface clock domain and two in the PCI clock domain, to post write data. Data can be written from the EC Interface at the same time write operation is running on the PCI bus.

The EC Interface-PCI Bridge core functions as a PCI target when accessed by an external PCI bus master. The PCI target contains two write buffers and a read buffer to handle write posting and to transfer data across the two clock domains. The request received from the PCI bus is forwarded upstream to a user interface port. Memory controller or other user logic can be connected to this interface port to process these PCI accesses.