Product Summary  



download 4 Lane PCI Express Endpoint Controller information EC314 4-Lane PCI-Express Bus Controller

See EC310 for 1-Lane PCI Express Endpoint Controller


  • Compliant to PCI Express Specification 1.1 for 4-lane end point.
  • Supports all 3 layers of PCI Express protocol.
  • Simple user interface to send and receive requests from the PCI Express Link with address and data bus.
  • Automatically generates and decodes all PCI Express packets and header information.
  • Handles all PCI Express protocols, ordering rules, flow control, LCRC, error checking, replay, scrambling and lane training.
  • Includes all PCI Express configuration and power management registers.
  • Lane reversal and polarity inversion are supported by the core.
  • Identical user interface as 1-lane IP core ease design migration.
  • High performance design delivers close to 100% of the theoretical bandwidth in real applications.
  • Multiple posted requests and pending request queues.
  • 4-lane design supports up to 10Gbps.
  • Optional AHB user interface and DMA transfer.
  • Synthesizable RTL code for ASIC and FPGA implementations.
  • Standard PIPE interface supports for on-chip PHY cores and external PHY chips.


4-Lane PCI Express Bus Controller block diagram