EC423 64-bit PCI-X Master/Target

Features

• Fully supports PCI and PCI-X protocol.
• Designed for ASIC and PLD implementations.
• Fully static design with edge triggered flip-flops.
• Efficient user interface for different types of user devices.
• User interface and PCI interface runs at different clock speed.
• Include data buffer and synchronization logic to bridge the two clock domains.
• Automatic detection of PCI and PCI-X bus systems.
• Combined bus master and target functions.
  • Master function
  • Initiate PCI memory and IO read/write.
  • Automatic transfer restart on target retry and disconnect.
  • Target function
  • Memory or IO read/write.
  • Configuration read/write.
  • Split transaction.
• Supports Zero wait state and user inserted wait state burst data transfer.
• Dual write buffer in each direction to support write data posting.
• Automatic handling of configuration register read/write access.
• Parity generation and parity error detection.
• Includes all PCI specific configuration registers.
• Supports high speed bus request and bus parking.

Diagram

Description

The EC423 64-bit PCI-X master/target core is optimized to operate in both PCI mode and PCI-X mode. The back-end interface is a highly efficient and flexible back-end bus which provides for easy integration with other user logic. This PCI-Xcore automatically switch between PCI and PCI-X protocol based on the system environment. It supports both PCI version 2.2 and PCI-X version 1.0.

The EC423 64-bit PCI-X master/target core is designed so that user interface can operate at any clock speed independent of the PCI bus speed. The user interface clock and PCI bus clock can be synchronous our asynchronous to each other. The PCI-X core utilizes double write buffer for write posting in both the master and target direction. The double data buffer design approach allows data access by the user interface and the PCI interface simultaneously and independent from each other.

When function as a master, the controller is capable of initiating memory or IO read and write upon user requests. The type of command and the burst size are specified by the user for each data transaction. Burst size can be determined by the user on a per transaction basis.

Once a master transfer begins, the core monitors the target device’s signals on the PCI and PCI-X bus and transfer data to the user logic. All different types of transfer terminations such as retry, disconnect and split response are handled by the PCI-X IP. If a transfer is retry or disconnected by the target, the master core re-starts the transfer automatically without the assistance of the user logic. Bus request, bus parking, parity detection and generation all are handled by the core. If a transaction is terminated with split response, the master would wait for the split completion transfer from the target.

The target controller is capable of handling memory and IO accesses on the PCI and PCI-X bus. All memory/IO accesses are supported. Configuration register read and write transactions are supported locally by the bus target without assistance from the user logic. Memory and I/O write to the target are posted in the write buffer before they are transferred to the user. Memory and I/O read are handled as delay read on PCI bus and as split transaction on PCI-X bus. The user interface allows the user to control the characteristics of the access. For example, the user can insert a wait state or transfer data without wait state according to its data bandwidth.