32-bit PCI Host Bridge
See EP420 for 64-bit PCI Host Bridge
- Fully supports PCI specification 2.1 and 2.2 protocol.
- Designed for ASIC and PLD implementations.
- Fully static design with edge triggered flip-flops.
- Efficient back-end interface for different types of user devices.
- Host bridge design includes bus master, bus target and central
- Generates standard PCI type 0 and type 1 configuration accesses.
- Combined bus master and target functions.
- Master function
- Initiate PCI memory and IO read/write.
- Automatic transfer restart on target retry and disconnect
- Target function
- Memory or IO read/write
- Configuration read/write
- Support for back-end initiated target retry, disconnect and
- Supports Zero wait state and user inserted wait state burst data
- Dual write buffer supports write data posting.
- User controlled burst and non-burst data transfer.
- Automatic handling of configuration register read/write access.
- Supports user initiated target retry, disconnect, abort and delayed
- Parity generation and parity error detection.
- Includes all PCI specific configuration registers.
- Supports high speed bus request and bus parking.
- Backend interface bus type and width selection.
- Bus arbiter with priority selection.
- Multiple base address registers.
- Asynchronous clock domain.
- Address/Data multiplexing.
- Backend FIFO interface.
- Unidirectional host bridge.
- Burst length and target burst.