SD 3.0/eMMC 4.5 Host Controller
- Host controller for SD and SDIO 3.0 with options to support eMMC 4.5 interface.
- Allows host CPU to access SD and MMC devices.
- Simple user interface optimized for on-chip bus connection.
- Choices of AHB, AXI, APB, PLB, Wishbone, Avalon, SH4 and generic user interface.
- Supports Ulta High Speed UHS interface including SDR104, SDR50, DDR50, SDR25 and SDR12.
- Supports programable clock mode to allow data transfer running at UHS while base clock at lower speed to save power.
- Input tuning and share bus configuration.
- Auto CMD23 command support.
- Supports SDMA operation for high speed data transfer without CPU polling of data.
- Implement SD host controller standard register set for support of standard SDIO development tool.
- 8-bit data transfer when eMMC option is included.
- Supports all standard SD/SDIO bus drivers including Windows and Linux.
- Fully programmable access timing.
- Hardware handling of CRC error detection and interrupt generation.
- Supports multi-function SD cards, command suspend, resume, and block transfers.
- Option to operate the user interface and card interface at different clock domains.
- Direct mapping of host address space to card address space.
- Designed for ASIC and FPGA implementations.
- Fully static design with edge triggered flip-flops.
- Choices of AXI, AHB, APB, PLB, Wishbone, Avalon, SH4 and generic user interface.
- Option to support eMMC 4.5 with 8-bit bus interface.
- Program clock mode allows the controller to operate at slow FPGA device and achieve UHS transfer rate at the same time.
- Asynchronous user interface.