Product Summary  

 

 

download eMMC 5.0 host controller informationEP555 eMMC 5.0 Host Controller

Features

  • Host controller for eMMC Interface with support compatible up to eMMC 5.0.
  • Choices of AHB, AXI, APB, PLB, Wishbone, Avalon, SH4 and generic user interface.
  • Supports HS400 for 400Mbyte/sec. Backward compatible to all lower eMMC speeds including HS200.
  • Supports programable clock mode to allow data transfer running at HS400 while base clock at lower speed to save power.
  • Input tuning and built-in double data buffer.
  • Supports SDMA operation for autonomous data transfer.
  • Implement SD host controller standard register set and supports all standard bus drivers including Windows and Linux.
  • 8-bit data transfer including DDR transfer mode.
  • Hardware handling of CRC error detection and interrupt generation.
  • Option to support SD cards including SDHC and SDXC and SDIO device.
  • Supports eMMC boot mode operation.
  • Includes softPHY to handle HS400 DDR data rate./li>

Differentiating Features

  • Choices of AXI, AHB, APB, PLB, Wishbone, Avalon, SH4 and generic user interface.
  • SoftPHY for different FPGA families.
  • Program clock mode allows the controller to operate at slow FPGA device and achieve UHS transfer rate at the same time.
  • Asynchronous user interface.

Diagram

eMMC 5.0 Host Controller block diagram