EP100 PowerPC Bus Slave

Features

• Fully supports PowerPC™ 60x bus protocol including PowerPC 603, 604, 740, 750 and MPC8260.
• Designed for ASIC or FPGA implementations in various system environments.
• Direct support for standard asynchronous SRAM and synchronous BURST SRAM.
• User interface bus for on-chip and off-chip user logic access.
• Variable wait state supported on user logic.
• Burst access supported on all interfaces.
• Process memory requests on the PowerPC bus.
• Handles separate address bus and data bus tenure.
• Supports PowerPC address pipeline for improve performance.
• Supports address bus retry generated by other external device.
• Address parity and data parity detection and generation.

Diagram

Description

The EP100 PowerPC bus slave device is a bus interface unit designed for the PowerPC host bus. It is designed to work on any 60x compliant bus architecture.

It has two user interfaces, one for interfacing with user logic and the second interface is a direct interface to external asynchronous SRAM and synchronous BURST SRAM.

The PowerPC bus slave works together with other slave devices or system controllers on the PowerPC bus. The slave can be assigned to specific address space where it is mapped into. Access to the slave device is further directed to either the SRAM interface or the user interface bus based on address mapping. The address mapping controller can be hardwired to the core or can be supplied by the user during run-time.

Both burst and single beat data transfer are supported on the SRAM and user logic interface.

The PowerPC bus slave supports advance features of the PowerPC bus including address pipeline, retry, separate address and data bus tenure to improve bus performance.

The following example shows the bus slave interface with on-chip user logic as well as 1 Mbyte memory system built by 128Kx8 standard SRAMs.