EP300 PowerPC Bus Arbiter

Features

• Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
• Designed for ASIC or PLD implementations in various system environments.
• Fully static design with edge triggered flip-flops.
• Supports up to eight PowerPC bus masters with unlimited slave device support.
• Supports two outstanding bus accesses.
• Supports address only transfer and address bus retry.
• Independent address bus and data bus tenure with separate bus grant and data bus grant.
• Option for fixed priority assignment or rotating priority scheme

Diagram

Description

The EP300 PowerPC bus arbiter provides all the necessary functions to arbitrate multiple bus masters directly connected to the PowerPC host bus. The arbiter supports separate address and data bus tenure to realize the high performance allowed by the PowerPC bus architecture. Separate address bus grant and data bus grant signal is provided for each master device on the bus. The PowerPC bus arbiter uses sophisticated built-in state machines to coordinate the address bus tenure and the data bus tenure. At any given cycle, up to two simultaneous bus accesses are allowed.

The EP300 PowerPC bus arbiter comes with the options of rotating priority or fixed priority schemes to meet the requirements for different system environments.