Product Summary  

 

 

EP534 AMBA AHB Bus to DDR SDRAM Controller

Features

  • External pin reduction by transferring 2 bits of data per pin.
  • Supports multiple external SDRAM banks.
  • Automatic refresh generation with programmable refresh intervals.
  • Self-refresh mode to reduce system power consumption.
  • Standard delay cells or user provided DLL for DQ and DQS alignment.
  • Integrated data buffer synchronizes user interface with DDR SDRAM data.
  • Operates on both discrete DDR SDRAM chips and DDR SDRAM DIMM.
  • Programmable memory size: 4, 8, and 16 bits per SDRAM.
  • Programmable SDRAM access timing parameters.
  • Automatic refresh generation with programmable refresh intervals.

Diagram

AMBA AHB bus to DDR SDRAM Controller

Description

The AHB bus DDR SDRAM controller provides high speed SDRAM for the system. It features two access ports. One port interfaces directly to the AHB bus and the other access port is optimized for system core logic such as DMA or PCI bus bridge.

The EP534 SDRAM controller contains built-in arbitration unit to allow both the AHB CPU and system core logic to share DDR SDRAM access. Rotating priority scheme ensures equal sharing of the memory bandwidth.

Data between the EP534 and the DDR SDRAM is transferred at both the rising edge and falling edge of the clock input. This creates very tight timing requirement for generating write data and sampling read data. The EP534 has a built-in data path that handles all the data generation and sampling tasks. For read access, data is sampled by the data path at double data rate. Data is then synchronized with the internal clock and transferred to the user interface one-word per clock cycle as normal data. For write access, data is received from the user interface at the normal one-word per clock data rate. The EP534 data path then re-synchronize the data and transfer them using the double data rate. The EP534 has several data path designs for different requirements. The use of user provided DLL delay element is supported but not necessary. Eureka provides programmable delay cell design for the alignment of DDR data.

The pipeline feature of the AHB-DDR SDRAM controller allows the user port to specify the next access address while the current data transfer is in progress. Multiple data transfers can be cascaded together to read or write data from the DDR SDRAM continuously, without any wasted cycle between accesses.

Another performance enhancement features of the AHB-DDR SDRAM controller is that it uses fast page access whether there is a row hit. For each of the four internal banks, the AHB-DDR SDRAM controller keeps the previous accessed row open. If the new request hits the same row, a column access is performance thus eliminate row access time. The DDR SDRAM controller simultaneously keeps track of four open rows, one for each bank.

The SDRAM controller can be programmed to support different sizes and configurations of SDRAMs. The SDRAM device sizes supported are 64Mbits, 128Mbits, 256mbits and 512Mbits. The data width per SDRAM device can be programmed to 4, 8 or 16 bits. The user can use multiple SDRAMs to build an wider memory subsystems.

The SDRAM controller is fully programmable. All access timing parameters such as CAS latency, row-to-column delay, refresh interval, etc., are programmable to support different speed grades of SDRAM devices and different operating frequencies. All the timing parameters can be modified during run-time by a separate access port. The timing parameters can also be set to the proper default values during compile time so that there is no need to program them during run-time.