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NAND Flash FAQ
What is NAND Flash?
NAND Flash is a type of memory device called nonvolatile memory. It is probably the most common nonvolatile memory used for mass storage. The following table classifies different types of silicon memories :
Type |
Subtype |
Example |
Volatile
Retain data only when power is on. Loss data when power is off
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Static memory
Retain data indefinitely as long as power is on. Consumes none or very little power to retain data
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SRAM such as CPU cache |
Dynamic memory
Retain data for a small period of time when power is on. Require periodic refresh to retain data. Consumes power during refresh
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SDRAM |
Nonvolatile
Retains data regardless of power supply
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Programmable memory
Data can be written into the device many times.
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NAND Flash
NOR Flash
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One-time programmable memory
Data can be written into the device only during the manufacturing process.
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Mask programmable ROM |
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Structural differences between NAND Flash and NOR Flash?
The biggest difference between NAND Flash and NOR Flash devices is the way that the memory cells are arranged. Both NAND and NOR Flash cells use single transistor memory cell. In NOR Flash, these cells are arranged in parallel with all the source node of the cells connected to the bit line, similar to the way that NMOS transistors are arranged in building a NOR gate. In NAND Flash, the cells are arranged in series with the adjacent cells sharing source and drain, similar to the way NMOS transistors are arranged in building a NAND gate. The sharing of the source and drain of adjacent cells eliminates the need for metal contact and tremendously reduces the die size. NAND Flash cells can be packed much closer together, with a 60% saving cell size over NOR Flash.
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What does NAND Flash controller do?
Due to the serial cell structure used in NAND Flash devices, data from the memory block are read serially. The disadvantage, as compared to NOR Flash or SRAM design, is that data cannot be randomly accessed. However, once a page of memory is opened for read, data can be shifted out from the memory much faster than in NOR Flash. The NAND Flash interface also requires that commands to the NAND Flash be sent serially to the device as a command packet, instead of the parallel "address" and "data" signals in typical SRAM. These are the major reasons that make interfacing with NAND Flash memory much more complicated than interfacing with typical SRAM or NOR Flash devices.
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How to send command to NAND Flash?
NAND Flash devices has 5 control signals (CS, ALE, CLE, RD, WE), 8 data signals and one response signal (R/B). Commands are shifted into the device through the data pins when CLE is active. If the command contains address, the address information are shifted into the device through the data signal when ALE is active. RD and WE are used to shift data into or out of the NAND Flash device. For command that requires long time to process, such as erase, or program, the R/B signal indicates when the device is busy.
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How are data stored in NAND Flash?
The basic unit of operation for NAND Flash device is one page of data with some commands affecting the whole block (64 pages) or the whole chip. Before programming, a page should be erased which sets all data bits to "1". Afterwards only the value "0" can be programmed into each cell. Programming effectively stores a new data with the value equal to the logical "AND" of the existing data and the program data.
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How to program a NAND Flash device?
NAND Flash devices are programmed on a page by page basis. The command word and the page address are first shifted into the device followed by the programming data. The exact programming steps of a NAND Flash device varies depending on whether it is large block or small block device and whether features such as two plane programming or cache mode are used. During programming, the R/B signal is low to indicate that the device is busy. Typical programming time is a few hundred micro second per page. Variations such as two plane programming, cache programming and random programming are supported by some NAND Flash devices.
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How to read data from a NAND Flash device?
NAND Flash devices are read by shifting in the command and address. After the command and address are shifted in, it takes a few tenths of micro second to open a page. After a page is opened, data can be shifted out of the device by using the RD command signal. Some devices support random data read within a page and some support cache read mode.
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What are the commands supported by NAND Flash devices?
There are many commands; some are manufacturer specific and supported only by a few devices while some commands are universal to all NAND Flash manufacturers. The most common commands are RESET, ERASE, PROGRAM, PROGRAM CONFIRMATION, READ DATA, READ STATUS and READ ID. Device specific commands include RANDOM READ, RANDOM WRITE, PAGE CACHE READ, PAGE CACHE WRITE, INTERNAL DATA MOVE, TWO-PLANES READ, TWO-PLANE WRITE, and others.
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Large block vs. small block.
NAND Flash devices can be categorized by large block and small block devices. From the user's perspective, it is more correct to call them as large page and small page devices. Large block device has 2048 bytes of data and 64 bytes of spare data per page while small block device has 512 bytes of data and 16 bytes of spare data per page. Commands sequence for large block and small block devices are different so the controller must be aware of which type of device is being used.
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What is spare column in NAND Flash?
NAND Flash devices organize 512bytes or 2048 bytes of data into a page. There are also 16 or 64 bytes of extra data called the spare column associated with each page. The spare columns are fully addressable by the user and is typically used for storing Error Correction Code (ECC) to improve data integrity.
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What is Error Correction Code (ECC)?
Due to manufacturing issues (yield), usage (wear and tear) and environmental factors, data stored in NAND Flash may not retain its value as written. However, the probability for this happening is very small so normally only very few number of bits contain the wrong value and the vast majority of the data bits are still correct. ECC is a good way to recover the wrong value from the remaining good data bits. NAND Flash manufacturers recommend the use of ECC for most NAND Flash applications where data reliability is factor.
For NAND Flash devices, the most common ways to implement ECC protection are: ECC per word and ECC per page. For ECC per word, it requires 7 ECC bits to be stored for each 32-bits of data. This allows the ECC circuit to correct 1 bad bit out of the 39 bits (32-bit data + 7-bit ECC) and detect two bad bits out of the 39 bits. This is called single bit correction and double bit detection. The ECC bits requires 25% overhead of memory storage. For ECC per page, 24 ECC bits are required for each 512-bytes of data. The error tolerance is much less compared to word ECC because it can correct only 1 bad bit out of the 4120 bits and detect two bad bits out of the 4120 bits. Typically page ECC bits are stored in the spare column area of the NAND Flash so no memory storage overhead is required. ECC protection on a page basis also requires that the entire page to be read or written so that the ECC information can be computed correctly.
To support ECC, the memory controller must have the capability to generate ECC bits to be stored in NAND Flash and to read back the ECC values from NAND Flash. After the values are read, the controller must be able to compute the ECC results and correct the read data or indicate the bad data location.
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What is bad block?
Like all large memory devices, not all the memory cells are fully functional due to yield related issues. Most memory devices use some kind of repair method to repair or remap the bad cells so that the memory device is fully functional from the user's perspective. NAND Flash devices handles this problem by declaring some blocks (a block is 64 pages of memory) as bad block. During production testing after wafer fab, each memory die is tested and bad blocks, if any, are marked at the spare column of the first 2 pages of the block. It is the responsibility of the user to read the bad block markings and to avoid using the bad blocks. Over the life time of the NAND Flash, additional bad blocks may develop due to repeated use of the memory cells so the user must be equipped to handle the new bad blocks. Typically bad block management is done by system software to remap data to avoid using bad blocks in the memory device.
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What is wear leveling?
NAND Flash cells, regardless how carefully they are designed and tested, have only limited lifetime. Typically, NAND Flash cells can be erased or programmed only about 100,000 times before they fail. If a particular page of data stored in NAND Flash is updated often, cells within that page can become useless after a very short time, rendering the entire system to fail. Wear-leveling is a technique that spreads the memory use evenly to different physical pages so that the entire NAND Flash devices is used evenly to maximize the life span of the device and the system. Similar to bad block management, wear leveling involves the remapping of logical address to different physical address of the device. Wear leveling and bad block management are typically done by software called Flash Transaction Layer (FTL). Many software vendors supply FTL software.
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What is RAM shadowing?
Due to the limited erase/program cycle and slow speed (compared to SDRAM) of NAND Flash devices, shadowing is a technique that system designers use to increase performance of the system. Portions of the NAND Flash device or the entire device is copied (shadowed) to SDRAM or SRAM during system initialization. Once copied, the system operates directly out of the SDRAM/SRAM. Data are copied back to the NAND Flash device only when they are modified and when it becomes necessary.
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Can NAND Flash be used as boot rom?
Yes, but some special design considerations are needed. Since NAND Flash data cannot be read until a page is opened, it cannot be used for CPU code fetch during boot up time. Special hardware must be built into the NAND Flash controller to open a page for read immediately after reset. A special boot up code must be written to the first page so that the CPU can fetch all the initial instructions within this page. The initial code must contain instructions for the CPU to access the remaining pages from the NAND Flash or to shadow the NAND Flash to SDRAM/SRAM.
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NAND Flash vs. Hard disk
In many applications where NAND Flash devices are used, such as USB drives and removable memory cards, the device is used as a hard drive instead of a linear memory space. For example, a 1Gbyte memory card does not appear to the system as 1Gbyte of storage as in the main memory (SDRAM). Instead it appears as a hard disk drive, with drive letter, directory name, file name, etc. This is done by the system software called the file system, which uses the storage space in the NAND Flash in the same manner as the system uses hard disk drive. Even though NAND Flash device is commonly used in this manner, the file system software is not related to the NAND Flash device at all. The file system is more related to the interface (USB, SD/SDIO, MMC, etc.) that connects the NAND Flash to the system. File system is typically part of the operating system but can also be provided separately by many system software vendors.
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