EC220 32-bit PCI Master/Target

See EC240 for 64-bit PCI Master/Target

Features

• Compliant with PCI specification 2.2/2.3/3.0 protocol.
• Designed for ASIC and FPGA implementations in various system environments.
• Combines bus master and bus target functions in one core.
• Supports burst transfer to maximize memory bandwidth.
• Zero wait state PCI data transfer. Up to 133Mbyte/sec at 33Mhz and 266Mbyte/sec at 66Mhz.
• Supports target retry, disconnect and target abort.
• Automatic transfer restart on target retry and disconnect.
• Concurrent bus master and target function.
• Write buffer for target write data posting to increase PCI bus performance.
• Responds to standard PCI configuration access.
• Supports all PCI specific configuration registers.
• User controlled base address register sizing and mapping.
• Retry counter to limit bus access to non-responsive target device.
• PCI status directly available to user logic for interrupt generation.
• Option for integrated DMA controller.
• Option for AMBA AHB and other CPU interface.

Diagram

Description

The EC220 32-bit PCI bus master/target core is optimized for different applications. The back-end interface is a highly efficient and flexible back-end bus which provides for easy integration with other user logic. This 32-bit PCI bus master/target core utilizes double data buffer design approach which minimizes design gate count and achieves highest possible data bandwidth at the same time.

The PCI bus master controller is capable of initiating memory or IO read and write upon back-end requests. The type of command and the burst size are specified by the user for each data transaction. Burst size can be pre-determined by the user for each transaction or changes as the transaction progress.

Once a master transfer begins, the core monitors the target device’s signals on the PCI bus and transfer data to the user logic. All different types of transfer termination are handled by the core. If a transfer is retry or disconnected by the target, the master core re-starts the transfer automatically without the assistance of the user logic. Bus request, bus parking, parity detection and generation all are handled by the core.

The PCI target controller is capable of handling memory and IO accesses on the PCI. All seven types of PCI memory/IO accesses are supported. Configuration register read and write transactions are supported locally by the bus target without assistance from the user logic.The user interface allows the user to control the characteristics of the access. For example, the user can insert wait state or transfer data without wait state according to its data bandwidth. Single or burst transfer, retry, disconnect, delay transaction and target abort can all be controlled by user logic.

Optional Features

The following table summarizes the optional features which can be provided with the 32-bit PCI bus master/target core as required by user application.