64-bit PCI-X Host Bridge
- Fully supports PCI 2.3 and PCI-X protocol 1.0b.
- Designed for ASIC and PLD implementations.
- Fully static design with edge triggered flip-flops.
- Efficient user interface for different types of user devices.
- User interface and PCI interface runs at different clock speed.
- User interface independent of PCI or PCI-X configuration.
- Include data buffer and synchronization logic to bridge the two clock domains.
- Automatic detection of PCI and PCI-X bus systems.
- Combined bus master and target functions including split completion.
- Host bridge function to initiate configuration access with internal CONFIG_ADDR and CONFIG_DATA registers.
- Supports Zero wait state and user inserted wait state burst data transfer.
- Dual write buffer in each direction to support write data posting.
- Automatic handling of configuration register read/write access.
- Parity generation and parity error detection.
- Includes all PCI and PCI-X specific configuration registers.
- Supports high speed bus request and bus parking.