EP600 UART

Features

• Functionally compatible with 16550.
• Supports Character (16450) and FIFO (16550) mode operations.
• Designed optimized for ASIC and PLD implementations.
• Synchronous design with edge triggered flip-flops based on system clock input.
• 16-byte FIFO for transmitter and receiver reduces the number of interrupt to the CPU.
• Holding register in non-FIFO mode eliminates the need for precise synchronization between the CPU and UART.
• Add or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data.
• Independently controlled transmit, receive, line status and data set interrupts.
• Programmable baud generator divides input clock by 2 to (2¹⁶ -1) and generates the 16X clock.
• Synchronous input sampling timed by internal receiver clock.
• MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD).
• Programmable features: 5 to 8 bit characters, even/odd parities and no parity, 1, 1.5 and 2 stop bits, programmable baud rate.
• False start bit detection.
• Complete status reporting capabilities.
• Line break generation and detection.
• Internal Loopback.

Diagram