Product Summary  



EP201 PowerPC Bus Master


  • Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
  • Designed for ASIC or PLD implementations in various system environments.
  • Fully static design with edge triggered flip-flops.
  • Automatic bus arbitration for address bus and data bus based on internal bus request.
  • Separate address bus and data bus tenure with individual grant signals.
  • Supports address bus retry and data transfer error.
  • Qualified address bus grant and data bus grant through the use of bus busy signals.
  • User specified burst data transfer and single beat data transfer.
  • Supports two back-end user request ports with built-in arbitration.
  • Efficient back-end bus for internal data transfer.
  • Supports bus parking.

Differentiating Features

  • Multi user interfac.
  • Data snooping.
  • Extended data transfer.


PowerPC Bus Master